The construction of an EEPROM proposed in related art is shown in FIG. 19. The EEPROM shown in FIG. 19 has a memory transistor and a select transistor for selecting this memory transistor at times of memory overwriting and reading.
In a region of the memory transistor, an embedded N-type layer 32 corresponding to a drain region and an N+-type source layer 42 are formed in a superficial layer of a semiconductor substrate 31. Also, a gate oxide film 33 is formed on the surface of the semiconductor substrate 31 and a tunnel film 34 is formed above the embedded N-type layer 32. A floating gate electrode 35, an interlayer insulating film 36 and a control gate electrode 37 are formed extending from above the tunnel film 34 to above the region between the embedded N-type layer 32 and the source layer 42.
In a region of the select transistor, a gate electrode 38 is formed on the gate oxide film 33 on the semiconductor substrate 31. And in the superficial layer of the semiconductor substrate 31 at the sides of the gate electrode 38, an N+-type source layer 41, a drain side field moderating layer 39 and an N+-type drain layer 40 are formed.
In an EEPROM having this kind of construction, in the memory transistor, the embedded N-type layer 32 is formed before the floating gate electrode 35 is formed, and the source layer 42 is formed after the formation of the control gate electrode 37. Because of this, the channel length of a channel region between the embedded N-type layer 32 and the source layer 42 below the floating gate electrode 35 is not determined by self-alignment. Consequently, there has been the problem that dispersion tends to arise in the transistor characteristics.
Also, the floating gate electrode 35 and the control gate electrode 37 are formed above the embedded N-type layer 32 of the memory transistor. Therefore, because the region where the embedded N-type layer 32 and the floating gate electrode 35 overlap is large, the parasitic capacitance between the floating gate electrode 35 and the drain region is large. Consequently, there has been the problem that the overwriting speed is low.
To ameliorate these problems, the kind of technology shown in FIG. 20 has been proposed (JP-A-58-115865 and JP-A-59-205763). An EEPROM of the construction shown in FIG. 20, compared to the construction shown in FIG. 19, has the floating gate electrode 35 and the control gate electrode 37 removed above the drain region of the memory transistor. And, a drain side field moderating layer 43 is formed in the superficial layer of the semiconductor substrate 31 below the region where the floating gate electrode 35 and the control gate electrode 37 have been removed.
With this technology, in the memory transistor, by ion implantation with the floating gate electrode 35 and the control gate electrode 37 used as a mask, the field moderating layer 43 on the drain region side and the source layer 42 can be formed using self-alignment. Consequently, channel length dispersion can be suppressed and dispersion in the transistor characteristics can be reduced. And, compared to the construction of FIG. 19, because the region where the floating gate electrode 35 and the drain region overlap can be reduced, the parasitic capacitance between the floating gate electrode 35 and the drain region can be lowered. By this means, the overwriting speed can be increased.
However, even with the technology shown in FIG. 20, there are the following problems. In the EEPROM manufacturing process, the floating gate electrode 35 and the control gate electrode 37 are formed as follows. First, a first polysilicon layer to constitute the floating gate electrode 35 is formed on the tunnel film 34 and the gate oxide film 33. Then, on an interlayer insulating layer on that, a second polysilicon layer to constitute the control gate electrode 37 is formed. And after that, the floating gate electrode 35, the interlayer insulating film 36 and the control gate electrode 37 are formed by etching the first polysilicon layer, the interlayer insulating layer and the second polysilicon layer simultaneously.
Thus, in the manufacture of the EEPROM shown in FIG. 20, a special working step of etching the three layers that are the first polysilicon layer, the interlayer insulating layer and the second polysilicon layer simultaneously is necessary.
And, the gate electrode of the select transistor also has a three-layer structure, made up of a first polysilicon layer 44, an interlayer insulating layer 45 and a second polysilicon layer 46. Consequently, there has been the problem that, to obtain electrical connection between the first polysilicon layer 44 forming the gate electrode and an external electrode, it is necessary to add a working step of forming a hole in the interlayer insulating layer 45 and the second polysilicon layer 46 above the first polysilicon layer 44.
And, when as shown in FIG. 20 the floating gate electrode 35 and the control gate electrode 37 are formed above only a part of the region of the tunnel film 34, at the time of the above-mentioned working of the three-layers, because the tunnel film 34 is exposed, etching damage is done to the tunnel film 34. Consequently, the problem arises that deterioration of the tunnel film 34 occurs and the overwriting life of the device falls.
And, when the three layers that are the first polysilicon layer, the interlayer insulating layer and the second polysilicon layer are etched simultaneously, the end faces of the interlayer insulating film 36 become exposed. When etching damage from the working mentioned above remains on these exposed end faces, the problem arises that, because the charge of the floating gate electrode 35 escapes through these damaged end faces, the charge holding characteristic deteriorates.